This invention relates to a transfer circuit used for operation test of LSI systems, and more particularly to a transfer circuit for operation test of LSI systems including general function blocks such as counter circuits, multipliers and arithmetic logic units (ALUs).
In the prior art, a Scan Path technique is known as a method for simplifying the operation test of LSI systems. In the Scan Path technique, D-type flip-flops or sequential circuits are serially connected to form a shift register. In the operation test, the shift register is used to supply plural items of test data to networks connected at the latter stage of the flip-flops and also to latch plural items of system data generated from networks connected at the preceding stage of the flip-flops. The test data items are serially supplied to an input terminal of the shift register and shifted in the shift register to be preset in corresponding flip-flops of the shift register. The latched system data items are shifted in the shift register to be supplied to the exterior from the output terminal and used to be compared with the expected value. In this case, the network of the LSI system is divided into smaller subnetworks and most of the subnetworks each form a combinational network.
FIG. 1 shows the prior art transfer circuit used for the operation test by the Scan Path technique. The transfer circuit is formed on the same semiconductor chip together with LSI system SY, for example. The transfer circuit includes scan registers SR-1 to SR-N which are constituted by flip-flops DF-1 to DF-N and data selectors SL-1 to SL-N in LSI system SY. Each of data selectors SL-1 to SL-N has first and second input terminals and is used to selectively supply one of input signals supplied to the first and second input terminals to D-input terminal of a corresponding one of flip-flops DF-1 to DF-N. Further, the first input terminals of data selectors SL-1 to S1-N are connected to receive system data generated from the subnetworks connected at the preceding stage of flip-flops DF-1 to DF-N, and the second input terminal of data selector of SL-1 is connected to scan input terminal SIN to which test data is supplied and data selectors SL-2 to S1-N are connected to receive output data OUT-1 to OUT-(N-1) from flip-flops DF-1 to DF-(N-1). Scan output terminal SOUT is provided to supply output data OUT-N of flip-flop DF-N to the exterior. The selection operations of data selectors SL-1 to SL-N are controlled by a control signal supplied via terminal CONT and the latch operations of flip-flops DF-1 to DF-N are controlled by a clock signal supplied via terminal CLK. Output data OUT-1 to OUT-N from flip-flops DF-1 to DF-N are further supplied to the latter stage subnetworks.
In order to operate LSI system in a normal fashion apart from the operation test, control signal CONT is set at "0" level and each of data selectors SL-1 to S1-N is so set to select input data supplied to the first input terminal or system data. In this case, flip-flops DF-1 to DF-N are operated to latch the system data at a rising of the clock signal and supply the system data as data output OUT-1 to OUT-N at a falling of the clock signal immediately after the rising thereof.
In the operation test for LSI system SY, control signal CONT is set at "1" level and each of data selectors SL-1 to SL-N is set to select input data supplied to the second input terminal. That is, LSI system SY is electrically isolated from scan registers SR-1 to SR-N. N test data are sequentially supplied to scan input terminal SIN in synchronism with clock signal CLK and latched in respective flip-flops DF-1 to DF-N. Under this condition, control signal CONT is set to "0" level. Then, flip-flops DF-1 to DF-N are operated in one clock cycle under a control of clock signal CLK. In this operation, flip-flops DF-1 to DF-N supply test data to the latter stage subnetworks and then latch system data generated from the preceding stage subnetworks. After this, control signal CONT is set to "1" level again and flip-flops DF-1 to DF-N are operated to sequentially supply system data to the exterior under the control of control signal CLK. Each system data is monitored and compared with the expected value. In the operation test, a combination of test data preset in flip-flops DF-1 to DF-N is repeatedly changed and the same comparison as described above is effected.
In general, the LSI system is designed by a plurality of circuit designers. Each circuit designer designs one of function blocks required to constitute the LSI system, for example, and confirms that the input and output characteristics of the function block satisfy the desired specification. At this time, a test sequence is formed to sequentially change the combination of test data and supply the test data to input terminals of the function blocks. Also, the expected value or a value which is to be generated from the output terminal of the function block according to the sequence is obtained by using a logic simulator. In a case where the Scan Path technique is used for the operation test of the LSI system, the LSI system is divided into subnetworks which are determined by the arrangement of D-type flip-flops DF-1 to DF-N. Since there is no special relation between the subnetworks and the function blocks, the test sequence and the expected value prepared by the circuit designer for attaining the above purpose cannot be used for the operation test of the entire LSI system.
In the case where a designer is required to divide a corresponding function block into subnetworks and prepare a test sequence and expected value therefor, each designer must take the other function blocks into consideration. In this case, it is particularly troublesome to obtain the expected value. For this reason, the expected value obtained cannot be used for the operation test of the entire LSI system until it is carefully checked.
Further, in the Scan Path technique, since it is necessary to entirely scan the LSI system, the number of circuit elements is increased, making it necessary to take an extremely long time for preparing the test sequence.